Spidev On Raspberry Pi For Ti Dac8568 Not Behaving As Expected

I have a Texas Instruments DAC8568 in their BOOST breakout board package. The DAC8568 is an 8 channel, 16bit DAC with SPI interface. The BOOST package has headers to connect it t

Solution 1:

Comment: the bits are shifted. ... how ... compensate for the shift or eliminate the shift?

This could be the case, if the SPIDIV.mode is not in sync with the DAC.

DAC Datasheet Page 6/7: This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shiftregister, and data are sampled on subsequent SYNC falling clock edges. The DAC output updates following the 32nd clock.

Reference: Clock polarity and phase

According to the above and the Timing Diagram I come to the conclusion that SPDIV.mode == 2 is the right.

1. Check the actual SPDIV.mode
2. Change to SPDIV.mode = 2

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I can confirm your used Values by reading Table 11 Page 35. Write to Input Register - DAC Channel X My Example set Feature Bits = 0

32110987654321098765432109876543210RXXXCCCCAAAADDDDDDDDDDDDDDDDFFFFA=32-bit[00000000000011111111111111110000]:0xffff0 ('0x00', '0x0f', '0xff', '0xf0')
            32110987654321098765432109876543210RXXXCCCCAAAADDDDDDDDDDDDDDDDFFFFB=32-bit[00000000000111111111111111110000]:0x1ffff0 ('0x00', '0x1f', '0xff', '0xf0')

Page 33: DB31(MSB) is the first bit that is loaded into the DAC shift register and must be always set to '0'.

The wireing seems straight forward and simple, but worth to doublecheck.

Code Snippet from testing:

def writeDAC(command, address, data, feature=0x0):
    address = ord(address) - ord('A')
    b1 = command
    b2 = address << 4 | data >> 12          # 4 address Bits and 4 MSB data Bits
    b3 = data >> 4                          # middle 8 Bits of data
    b4 = 0xF0 & (data << 4) >> 8 | feature  # 4 data Bits and feature Bits
    voltage_write = spi.xfer2([b1, b2, b3, b4])

# Usage:# Write Command=0 Channel=B Data=0xFFFF Default Features=0x0
writeDAC(0, 'B', 0xFFFF)